Technical Field
The present invention relates to contacts over a semiconductor substrate and methods of forming the same. More specifically, the present invention relates to forming an intermix region at an interface of a bottom portion of contacts and an upper portion of the semiconductor substrate, respectively.
Related Art
State of the art field effect transistors (FETs) can be fabricated by depositing a gate conductor over a gate dielectric and a semiconductor substrate. Generally, the FET fabrication process implements lithography and etching processes to define the gate structures. After providing the gate structures, source/drain extensions may be formed into a portion of the semiconductor substrate and on both sides of each gate structure by ion implantation. Sometimes this implant is performed using a spacer to create a specific distance between the gate structure and the implanted junction. Source and drain may be doped with a p-type or n-type dopant. The term “p-type” refers to the addition of impurities to an intrinsic semiconductor that creates deficiencies of valence electrons. “N-type” refers to the addition of impurities that contributes free electrons to an intrinsic semiconductor. After formation of the transistor, a set of contact openings may be created to expose the source and drain. The contact openings may be coated with a Ti-based silicide liner. Subsequently, contact openings may be filled with a metal material, such as W.
In a p-type FET (PFET), performance with a Ti-based silicide liner is a challenge for 14/10 nm silicon-on-insulator (14/10 SOI) technologies. In order to improve workfunction of Ti-based silicide in the source and drain of a PFET, a bilayer of NiPt and Ti has been employed to coat contact openings over the source and drain. However, this bilayer requires deposition of a relatively thick metal layer. As semiconductor devices get smaller, requiring a thick bilayer in the contact causes contact opening fill issues, such as an incomplete contact fill.